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1

[IEEE IEEE International Conference on Test, 2005. - Charlotte, NC, USA (Nov. 8, 2005)] IEEE International Conference on Test, 2005. - Test compression and logic BIST at your fingertips

Shianling Wu,, Laung-Terng Wang,, Jin Woo Cho,, Zhigang Jiang,, Boryau Sheu,

Année:

2005

Langue:

english

Fichier:

PDF, 318 KB

english, 2005

2

Low Capture Switching Activity Test Generation for Reducing IR-Drop in At-Speed Scan Testing

Xiaoqing Wen, Kohei Miyase, Tatsuya Suzuki, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja, Kozo Kinoshita

Journal:

Journal of Electronic Testing

Année:

2008

Langue:

english

Fichier:

PDF, 339 KB

english, 2008

3

Testing of Synchronizers in Asynchronous FIFO

Hyoung-Kook Kim, Laung-Terng Wang, Yu-Liang Wu…

Journal:

Journal of Electronic Testing

Année:

2013

Langue:

english

Fichier:

PDF, 743 KB

english, 2013

4

System-on-Chip Test Architectures || Introduction

Wang, Laung-Terng (L.-T.)

Année:

2008

Langue:

english

Fichier:

PDF, 892 KB

english, 2008

5

Launch-on-Shift Test Generation for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains

Wu, Shianling, Wang, Laung-Terng, Wen, Xiaoqing, Jone, Wen-Ben, Hsiao, Michael S., Li, Fangfang, Li, James Chien-Mo, Huang, Jiun-Lang

Journal:

ACM Transactions on Design Automation of Electronic Systems

Année:

2012

Langue:

english

Fichier:

PDF, 1.30 MB

english, 2012

6

Fault Modeling and Analysis for Resistive Bridging Defects in a Synchronizer

Hyoung-Kook Kim, Wen-Ben Jone, Laung-Terng Wang

Journal:

Journal of Electronic Testing

Année:

2010

Langue:

english

Fichier:

PDF, 861 KB

english, 2010

7

Condensed Linear Feedback Shift Register (LFSR) Testing—A Pseudoexhaustive Test Technique

Laung-Terng Wang, McCluskey, E.J.

Journal:

IEEE Transactions on Computers

Année:

1986

Langue:

english

Fichier:

PDF, 870 KB

english, 1986

8

Using Launch-on-Capture for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains

Shianling Wu, Laung-Terng Wang, Xiaoqing Wen, Zhigang Jiang, Lang Tan, Yu Zhang, Yu Hu, Wen-Ben Jone, Hsiao, M.S., Li, J.C.-M., Jiun-Lang Huang, Lizhen Yu

Journal:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Année:

2011

Langue:

english

Fichier:

PDF, 410 KB

english, 2011

9

Using Launch-on-Capture for Testing BIST Designs Containing Synchronous and Asynchronous Clock Domains

Laung-Terng Wang, Xiaoqing Wen, Shianling Wu, Furukawa, H., Hao-Jan Chao, Boryau Sheu, Jianghao Guo, Wen-Ben Jone

Journal:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Année:

2010

Langue:

english

Fichier:

PDF, 709 KB

english, 2010

10

VirtualScan: Test Compression Technology Using Combinational Logic and One-Pass ATPG

Laung-Terng Wang, Xiaoqing Wen, Shianling Wu, Zhigang Wang, Zhigang Jiang, Boryau Sheu, Xinli Gu

Journal:

IEEE Design & Test of Computers

Année:

2008

Langue:

english

Fichier:

PDF, 569 KB

english, 2008

11

Turbo1500: Core-Based Design for Test and Diagnosis

Laung-Terng Wang, Apte, R., Shianling Wu, Boryau Sheu, Wen-Ben Jone, Jianghao Guo, Kuen-Jong Lee, Wei-Shin Wang, Xiaoqing Wen, Hao-Jan Chao, Jinsong Liu, Yanlong Niu, Yi-Chih Sung, Chi-Chun Wang, Fang

Journal:

IEEE Design & Test of Computers

Année:

2009

Langue:

english

Fichier:

PDF, 297 KB

english, 2009

12

[IEEE IEEE International Conference on Test, 2005. - Charlotte, NC, USA (Nov. 8, 2005)] IEEE International Conference on Test, 2005. - Low-capture-power test generation for scan-based at-speed testing

Xiaoqing Wen,, Yamashita, Y., Morishima, S., Kajihara, S., Laung-Terng Wang,, Saluja, K.K., Kinoshita, K.

Année:

2005

Langue:

english

Fichier:

PDF, 223 KB

english, 2005

13

[IEEE 2013 IEEE International Test Conference (ITC) - Anaheim, CA, USA (2013.09.6-2013.09.13)] 2013 IEEE International Test Conference (ITC) - A circular pipeline processing based deterministic parallel test pattern generator

Yeh, Kuen-Wei, Huang, Jiun-Lang, Chao, Hao-Jan, Wang, Laung-Terng

Année:

2013

Langue:

english

Fichier:

PDF, 308 KB

english, 2013

14

[IEEE Comput. Soc 23rd IEEE VLSI Test Symposium - Palm Springs, CA, USA (1-5 May 2005)] 23rd IEEE VLSI Test Symposium (VTS'05) - On low-capture-power test generation for scan testing

Xiaoqing Wen,, Yamashita, Y., Kajihara, S., Laung-Terng Wang,, Saluja, K.K., Kinoshita, K.

Année:

2005

Langue:

english

Fichier:

PDF, 161 KB

english, 2005

15

[IEEE IEEE International Conference on Test, 2005. - Charlotte, NC, USA (Nov. 8, 2005)] IEEE International Conference on Test, 2005. - Ultrascan: using time-division demultiplexing/multiplexing (TDDM/TDM) with virtualscan for test cost reduction

Laung-Terng L.-T. Wang,, Abdel-Hafez, K.S., Xiaoqing Wen,, Boryau Sheu,, Shianling Wu,, Shyh-Horng Lin,, Ming-Tung Chang,

Année:

2005

Langue:

english

Fichier:

PDF, 259 KB

english, 2005

16

[IEEE 2011 IEEE International Test Conference (ITC) - Anaheim, CA, USA (2011.09.20-2011.09.22)] 2011 IEEE International Test Conference - A novel scan segmentation design method for avoiding shift timing failure in scan testing

Yamato, Yuta, Wen, Xiaoqing, Kochte, Michael A., Miyase, Kohei, Kajihara, Seiji, Wang, Laung-Terng

Année:

2011

Langue:

english

Fichier:

PDF, 1.08 MB

english, 2011

17

[IEEE 2006 International Conference on Computer Design - San Jose, CA, USA (2007.10.1-2007.10.4)] 2006 International Conference on Computer Design - A Highly-Guided X-Filling Method for Effective Low-Capture-Power Scan Test Generation

Wen, Xiaoqing, Miyase, Kohei, Suzuki, Tatsuya, Yamato, Yuta, Kajihara, Seiji, Wang, Laung-Terng, Saluja, Kewal K.

Année:

2006

Langue:

english

Fichier:

PDF, 452 KB

english, 2006

18

[IEEE 2009 Asian Test Symposium - Taichung, Taiwan (2009.11.23-2009.11.26)] 2009 Asian Test Symposium - Analysis of Resistive Bridging Defects in a Synchronizer

Kim, Hyoung-Kook, Jone, Wen-Ben, Wang, Laung-Terng, Wu, Shianling

Année:

2009

Langue:

english

Fichier:

PDF, 379 KB

english, 2009

19

[IEEE 2011 IEEE 24th International SOC Conference (SOCC) - Taipei, Taiwan (2011.09.26-2011.09.28)] 2011 IEEE International SOC Conference - “Introduction to SoC testing”

Wang, Laung-Terng

Année:

2011

Langue:

english

Fichier:

PDF, 461 KB

english, 2011

20

[IEEE 2006 IEEE International Test Conference - Santa Clara, CA, USA (2006.10.22-2006.10.27)] 2006 IEEE International Test Conference - A Novel and Practical Control Scheme for Inter-Clock At-Speed Testing

Furukawa, Hiroshi, Wen, Xiaoqing, Wang, Laung-terng, Sheu, Boryau, Jiang, Zhigang, Wu, Shianling

Année:

2006

Langue:

english

Fichier:

PDF, 400 KB

english, 2006

21

[IEEE 2012 13th International Symposium on Quality Electronic Design (ISQED) - Santa Clara, CA, USA (2012.03.19-2012.03.21)] Thirteenth International Symposium on Quality Electronic Design (ISQED) - Physical-design-friendly hierarchical logic built-in self-test—A case study

Nelson, Kelvin, Shanmugavadivelu, Jaga, Mekkoth, Jayanth, Ghanta, Venkat, Wu, Jun, Zhuang, Fe, Chao, Hao-Jan, Wu, Shianling, Rao, Jie, Yu, Lizhen, Wang, Laung-Terng

Année:

2012

Langue:

english

Fichier:

PDF, 292 KB

english, 2012

22

[IEEE 24th IEEE VLSI Test Symposium - Berkeley, CA, USA (30-04 April 2006)] 24th IEEE VLSI Test Symposium - A New ATPG Method for Efficient Capture Power Reduction During Scan Testing

Xiaoqing Wen,, Kajihara, S., Miyase, K., Suzuki, T., Saluja, K.K., Laung-Terng Wang,, Abdel-Hafez, K.S., Kinoshita, K.

Année:

2006

Langue:

english

Fichier:

PDF, 356 KB

english, 2006

23

[IEEE 2008 23rd IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFTVS) - Cambridge, MA, USA (2008.10.1-2008.10.3)] 2008 IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems - On Optimizing Fault Coverage, Pattern Count, and ATPG Run Time Using a Hybrid Single-Capture Scheme for Testing Scan Designs

Wu, Shianling, Wang, Laung-Terng, Jiang, Zhigang, Song, Jiayong, Sheu, Boryau, Wen, Xiaoqing, Hsiao, Michael S., Li, James C.-M., Huang, Jiun-Lang, Apte, Ravi

Année:

2008

Langue:

english

Fichier:

PDF, 343 KB

english, 2008

24

[IEEE 2007 16th Asian Test Symposium - Beijing (2007.10.8-2007.10.11)] 16th Asian Test Symposium (ATS 2007) - An On-Chip Test Clock Control Scheme for Multi-Clock At-Speed Testing

Xiao-Xin Fan,, Yu Hu,, Laung-Terng Wang,

Année:

2007

Langue:

english

Fichier:

PDF, 330 KB

english, 2007

25

[IEEE 2010 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT) - Kyoto, Japan (2010.10.6-2010.10.8)] 2010 IEEE 25th International Symposium on Defect and Fault Tolerance in VLSI Systems - Logic BIST Architecture Using Staggered Launch-on-Shift for Testing Designs Containing Asynchronous Clock Domains

Wu, Shianling, Wang, Laung-Terng, Yu, Lizhen, Furukawa, Hiroshi, Wen, Xiaoqing, Jone, Wen-Ben, Touba, Nur A., Zhao, Feifei, Liu, Jinsong, Chao, Hao-Jan, Li, Fangfang, Jiang, Zhigang

Année:

2010

Langue:

english

Fichier:

PDF, 326 KB

english, 2010

26

[IEEE 2010 28th VLSI Test Symposium (VTS) - Santa Cruz, CA, USA (2010.04.19-2010.04.22)] 2010 28th VLSI Test Symposium (VTS) - CSER: BISER-based concurrent soft-error resilience

Wang, Laung-Terng, Touba, Nur A., Jiang, Zhigang, Wu, Shianling, Huang, Jiun-Lang, Li, James Chien-Mo

Année:

2010

Langue:

english

Fichier:

PDF, 545 KB

english, 2010

27

[IEEE 2010 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT) - Kyoto, Japan (2010.10.6-2010.10.8)] 2010 IEEE 25th International Symposium on Defect and Fault Tolerance in VLSI Systems - Hybrid Built-In Self-Test Architecture for Multi-port Static RAMs

Yu, Lizhen, Hung, Jeffrey, Sheu, Boryau, Huynh, Bill, Nguyen, Loc, Wu, Shianling, Wang, Laung-Terng, Wen, Xiaoqing

Année:

2010

Langue:

english

Fichier:

PDF, 340 KB

english, 2010

28

[IEEE 2006 15th Asian Test Symposium - Fukuoka, Japan (2006.11.20-2006.11.20)] 2006 15th Asian Test Symposium - Test Data Compression Based on Clustered Random Access Scan

Hu, Yu, Li, Cheng, Li, Jia, Han, Yin-he, Li, Xiao-wei, Wang, Wei, Li, Hua-wei, Wang, Laung-terng(l.t), Wen, Xiao-qing

Année:

2006

Langue:

english

Fichier:

PDF, 250 KB

english, 2006

29

[IEEE 2014 19th IEEE European Test Symposium (ETS) - Paderborn, Germany (2014.5.26-2014.5.30)] 2014 19th IEEE European Test Symposium (ETS) - GPU-based timing-aware test generation for small delay defects

Liao, Kuan-Yu, Chen, Po-Juei, Lin, Ang-Feng, Li, James Chien-Mo, Hsiao, Michael S., Wang, Laung-Terng

Année:

2014

Langue:

english

Fichier:

PDF, 401 KB

english, 2014

30

[IEEE ICCAD 2004. International Conference on Computer Aided Design - San Jose, CA, USA (7-11 Nov. 2004)] IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004. - On per-test fault diagnosis using the X-fault model

Xiaoqing Wen,, Tokiharu Miyoshi,, Seiji Kajihara,, Laung-Terng Wang,, Saluja, K.K., Kinoshita, K.

Année:

2004

Langue:

english

Fichier:

PDF, 616 KB

english, 2004

31

[IEEE 2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT) - Chicago, Illinois, USA (2009.10.7-2009.10.9)] 2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems - Analysis of Resistive Open Defects in a Synchronizer

Kim, Hyoung-Kook, Jone, Wen-Ben, Wang, Laung-Terng

Année:

2009

Langue:

english

Fichier:

PDF, 314 KB

english, 2009

32

[IEEE 2007 IEEE International Test Conference - Santa Clara, CA, USA (2007.10.21-2007.10.26)] 2007 IEEE International Test Conference - A novel scheme to reduce power supply noise for high-quality at-speed scan testing

Xiaoqing Wen,, Kohei Miyase,, Seiji Kajihara,, Tatsuya Suzuki,, Yuta Yamato,, Girard, Patrick, Yuji Ohsumi,, Laung-Terng Wang,

Année:

2007

Langue:

english

Fichier:

PDF, 415 KB

english, 2007

33

[IEEE 16th Asian Test Symposium (ATS 2007) - Beijing, China (2007.10.8-2007.10.11)] 16th Asian Test Symposium (ATS 2007) - Next Generation Test, Diagnostics and Yield Challenges for EDA, ATE, IP and Fab - A Perspective from All Sides

Kohiyama, Yasuharu, Ravikumar, C. P., Sato, Yasuo, Wang, Laung-Terng, Zorian, Yervant

Année:

2007

Langue:

english

Fichier:

PDF, 267 KB

english, 2007

34

LCTI–SS: Low-Clock-Tree-Impact Scan Segmentation for Avoiding Shift Timing Failures in Scan Testing

Yamato, Yuta, Miyase, Kohei, Kajihara, Seiji, Xiaoqing Wen,, Laung-Terng Wang,, Kochte, Michael A.

Journal:

IEEE Design and Test

Année:

2013

Langue:

english

Fichier:

PDF, 907 KB

english, 2013

35

[IEEE 2008 IEEE International Test Conference - Santa Clara, CA (2008.10.28-2008.10.30)] 2008 IEEE International Test Conference - Turbo1500: Toward Core-Based Design for Test and Diagnosis Using the IEEE 1500 Standard

Laung-Terng Wang,, Apte, R., Shianling Wu,, Boryau Sheu,, Kuen-Jong Lee,, Xiaoqing Wen,, Jone, W.-B., Chia-Hsien Yeh,, Wei-Shin Wang,, Hao-Jan Chao,, Jianghao Guo,, Jinsong Liu,, Yanlong Niu

Année:

2008

Langue:

english

Fichier:

PDF, 341 KB

english, 2008

36

[IEEE 2013 26th International Conference on VLSI Design: concurrently with the 12th International Conference on Embedded Systems - Pune, India (2013.01.5-2013.01.10)] 2013 26th International Conference on VLSI Design and 2013 12th International Conference on Embedded Systems - On Guaranteeing Capture Safety in At-Speed Scan Testing with Broadcast-Scan-Based Test Compression

Enokimoto, Kazunari, Wen, Xiaoqing, Miyase, Kohei, Huang, Jiun-Lang, Kajihara, Seiji, Wang, Laung-Terng

Année:

2013

Langue:

english

Fichier:

PDF, 319 KB

english, 2013

37

[IEEE 2008 17th Asian Test Symposium (ATS) - Hokkaido, Japan (2008.11.24-2008.11.27)] 2008 17th Asian Test Symposium - Practical Challenges in Logic BIST Implementation Case Studies

Wu, Shianling, Furukawa, Hiroshi, Sheu, Boryau, Wang, Laung-Terng, Chao, Hao-Jan, Yu, Lizhen, Wen, Xiaoqing, Murakami, Michio

Année:

2008

Langue:

english

Fichier:

PDF, 196 KB

english, 2008

38

Scan Flip-Flop Grouping to Compress Test Data and Compact Test Responses for Launch-on-Capture Delay Testing

Xiang, Dong, Chen, Zhen, Wang, Laung-Terng

Journal:

ACM Transactions on Design Automation of Electronic Systems

Année:

2012

Langue:

english

Fichier:

PDF, 337 KB

english, 2012

39

[IEEE 2015 IEEE 24th Asian Test Symposium (ATS) - Mumbai, India (2015.11.22-2015.11.25)] 2015 IEEE 24th Asian Test Symposium (ATS) - SDC-TPG: A Deterministic Zero-Inflation Parallel Test Pattern Generator

Chang, Chun-Hao, Yeh, Kuen-Wei, Huang, Jiun-Lang, Wang, Laung-Terng

Année:

2015

Langue:

english

Fichier:

PDF, 266 KB

english, 2015

40

[IEEE 16th Asian Test Symposium (ATS 2007) - Beijing, China (2007.10.8-2007.10.11)] 16th Asian Test Symposium (ATS 2007) - An On-Chip Test Clock Control Scheme for Multi-Clock At-Speed Testing

FAN, Xiao-Xin, HU, Yu, WANG, Laung-Terng (L.-T.)

Année:

2007

Langue:

english

Fichier:

PDF, 330 KB

english, 2007

41

[IEEE 16th Asian Test Symposium (ATS 2007) - Beijing, China (2007.10.8-2007.10.11)] 16th Asian Test Symposium (ATS 2007) - Next Generation Test, Diagnostics and Yield Challenges for EDA, ATE, IP and Fab - A Perspective from All Sides

Kohiyama, Yasuharu, Ravikumar, C. P., Sato, Yasuo, Wang, Laung-Terng, Zorian, Yervant

Année:

2007

Langue:

english

Fichier:

PDF, 267 KB

english, 2007

42

CPP-ATPG: A Circular Pipeline Processing Based Deterministic Parallel Test Pattern Generator

Yeh, Kuen-Wei, Huang, Jiun-Lang, Wang, Laung-Terng

Journal:

Journal of Electronic Testing

Année:

2016

Langue:

english

Fichier:

PDF, 2.29 MB

english, 2016

43

Low-Power Scan-Based Built-In Self-Test Based on Weighted Pseudorandom Test Pattern Generation and Reseeding

Xiang, Dong, Wen, Xiaoqing, Wang, Laung-Terng

Journal:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Année:

2016

Langue:

english

Fichier:

PDF, 1.98 MB

english, 2016

44

High Launch Switching Activity Reduction in At-Speed Scan Testing Using CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme

MIYASE, Kohei, WEN, Xiaoqing, FURUKAWA, Hiroshi, YAMATO, Yuta, KAJIHARA, Seiji, GIRARD, Patrick, WANG, Laung-Terng, TEHRANIPOOR, Mohammad

Journal:

IEICE Transactions on Information and Systems

Année:

2010

Langue:

english

Fichier:

PDF, 1.73 MB

english, 2010

45

On Achieving Capture Power Safety in At-Speed Scan-Based Logic BIST

TOMITA, Akihiro, WEN, Xiaoqing, SATO, Yasuo, KAJIHARA, Seiji, MIYASE, Kohei, HOLST, Stefan, GIRARD, Patrick, TEHRANIPOOR, Mohammad, WANG, Laung-Terng

Journal:

IEICE Transactions on Information and Systems

Année:

2014

Langue:

english

Fichier:

PDF, 3.48 MB

english, 2014

46

Electronic Design Automation || Test synthesis

Wang, Laung-Terng (L.-T.)

Année:

2009

Langue:

english

Fichier:

PDF, 414 KB

english, 2009

47

VLSI Test Principles and Architectures || Logic Built-In Self-Test

Wang, Laung-Terng (L.-T.)

Année:

2006

Langue:

english

Fichier:

PDF, 916 KB

english, 2006

48

VLSI Test Principles and Architectures || Design for Testability

Wang, Laung-Terng (L.-T.)

Année:

2006

Langue:

english

Fichier:

PDF, 1.07 MB

english, 2006